
SV51007
2014.01.10
Document Revision History
6-35
Date
December 2012
Version
2012.12.28
Changes
? Reorganized content and updated template.
? Added Altera_PLL settings for external PLL usage in DPA and non-
DPA modes.
? Moved the PLL and clocking section into design guideline topics.
? Updated external PLL clocking examples without DPA and soft-CDR.
Altera_PLL now supports entering negative phase shift.
? Added external PLL clocking example and settings for DPA and soft-
CDR mode.
? Updated the LVDS channel tables to list the number of channels per
side for each device package instead of just for the largest package.
? Removed the “ LVDS Direct Loopback Mode ” section.
June 2012
1.4
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?
?
?
Added Table 6 – 2.
Updated Table 6 – 1, Table 6 – 3, Table 6 – 4, and Table 6 – 5.
Updated Figure 6 – 21.
Updated “ Non-DPA Mode ” , “ Soft-CDR Mode ” , and “ PLLs and Stratix
V Clocking ” sections.
November 2011
1.3
? Updated Table 6 – 2.
? Updated Example 6 – 1.
? Updated “ LVDS Direct Loopback Mode ” and “ LVDS Interface with the
Use External PLL Option Enabled ” sections.
May 2011
1.2
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?
?
?
?
Chapter moved to volume 2 for the 11.0 release.
Added Table 6 – 2 and Table 6 – 3.
Updated Table 6 – 1.
Updated Figure 6 – 2 and Figure 6 – 23.
Updated “ Locations of the I/O Banks ” , “ Programmable Pre-Emphasis ” ,
“ Differential Receiver ” , “ Fractional PLLs and Stratix V Clocking ” , and
“ DPA-Enabled Channels, DPA-Disabled Channels, and Single-Ended
I/Os ” sections.
? Minor text edits.
December 2010
July 2010
1.1
1.0
No changes to the content of this chapter for the Quartus II software 10.1.
Initial release.
High-Speed Differential I/O Interfaces and DPA in Stratix V Devices
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